The invention relates to the field of signal processing, and in particular to recovering a carrier for a synchronous demodulator.
In order to transmit a signal, especially through a wireless interface, the signal is modulated before transmission. Demodulation is implemented on the receiver side. In order to demodulate the signal using a synchronous demodulator, it is necessary to reconstruct the carrier signal or the carrier for the signal. The received signal is then mixed with this reconstructed carrier into the baseband using an I/Q mixer, and demodulated therewith. A phase-locked loop (PLL) is used to reconstruct the carrier in the process of carrier recovery. This loop measures the current phase difference between the received and reconstructed carrier to calculate a control correction signal for the phase therefrom, this correction signal is used to track the reconstructed signal.
The maximum speed of the phase-locked loop, the so-called PLL bandwidth, is limited by the propagation times that occur within the control loop. In control engineering, these propagation times are called dead times. They reduce the maximum possible loop gains at which the system continues to operate in a stable fashion. However, if the received signal contains components lying outside the PLL bandwidth, a residual phase error remains. This error causes a reduction in the level of demodulation, thereby causing the signal to be demodulated incorrectly.
The disadvantage is thus that error-free demodulation cannot be effected due to this residual phase error. For this reason, an appropriately improved method or circuit for recovering the carrier is proposed.
FIG. 4 is a block diagram illustrating a known synchronous demodulator. A received input signal is applied on a line 402 to an I/Q mixer 404 (I: in-phase, Q: quadrature phase). The mixer 404 uses two multipliers 406, 408 to multiply the input signal on the line 402 with a locally reconstructed picture carrier or signal carrier in the form of a carrier on a line 410, and thus mixes the input signal into the baseband. During multiplication, mixing products are created which are located at double the carrier frequency. These mixing products are undesirable and are therefore filtered out within the mixer 404 by low-pass filters 412, 414. At the output of the mixer 404, the carrier is approximately at a frequency of f≈0. What is thus output is a mixed signal i, q, with in-phase and quadrature-phase components I, Q.
Referring still to FIG. 4, the mixed signal i, q is also supplied to a PLL control loop 416. The in-phase and quadrature signal components are input to low pass filters 418, 420, respectively. To remove audio information in the case of a television signal, the filtered mixed signal is applied to a so-called COordinate Rotation DIgital Computer (CORDIC). Using a polar coordinate transformation, the CORDIC 421 determines the phase value of the I/Q signal pair at the input, and provides the phase value on a line 422. If the reconstructed carrier on the line 410 equals the received carrier of the input signal on the line 402 exactly, then the measured phase on the line 422 is equal to zero. If this is not true, the phase value on the line 422 is used to correct a digital I/Q oscillator 424. This digital oscillator LO 424 generates the carrier on the line 410 which is supplied to the mixer 404 to be mixed with input signal on the line 402. For this purpose, the phase value on the line 422 is fed by the CORDIC 421 to a control device 426 which performs the appropriate calculations and controls the oscillator 424 accordingly.
In an implementation as a digital circuit, the necessary calculations within this type of control loop, also called an All Digital PLL (ADPLL), (e.g., calculations such as those performed by a CORDIC algorithm, filtering, and calculation of a correction signal by the control device 426), produce signal delays due to the calculation time and group propagation times of the filters. These delays are often called dead times in control engineering and reduce the maximum possible loop gain and thus the speed of the control loop. If in this case an excessively high loop gain is selected, the control loop becomes unstable. To characterize the speed of an ADPLL, the PLL-bandwidth is used which is obtained from the system transfer function. This indicates which frequency changes can still be compensated.
FIG. 5 illustrates the simulation of a signal in which the picture carrier contains unwanted frequency modulation. The frequency of the picture carrier here changes very quickly as soon as the amplitude changes. Since in this circuit the carrier recovery is not able to react quickly enough, the frequency change manifests itself as a rotation, meaning that the phase error becomes increasingly larger until the amplitude, and thus the frequency, change back to the original state.
FIG. 6 shows that the actual outputted demodulated signal demonstrates a response which clearly deviates from the ideal response. The signal example here is a video signal having a black picture content. The horizontal synchronization pulses of an ideal signal would be rectangular and free of high-frequency noise components. The simulated demodulated signal, on the other hand, reveals a high noise component and oblique edges with strong high-frequency oscillation components. For a connected television set, these distortions of the synchronization pulses mean that the horizontal alignment of the scanning lines cannot be precisely determined—with the resulting distorted picture contents.
There is a need for improved recovery of a carrier which takes into account the residual phase error.